Low-Cost Digital Detection of Parametric Faults in Cascaded Σ∆ Modulators

The test of Σ∆ modulators is cumbersome due to the high performance they reach. Moreover, technology scaling trends raise serious doubts on the intra-die repeatability of devices. Increase of variability will lead to an increase in parametric faults difficult to detect. In this paper, a designoriented testing approach is proposed to perform simple and low-cost detection of variations in important design variables of cascaded Σ∆ modulators. The digital tests could be integrated in a production test flow to improve fault coverage and bring data for silicon debug. A study is presented to tailor signature generation, with test time minimization in mind, as function of the desired measurement precision. The developments are supported by experimental results that validate the proposal.